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apic: make msr-related function names consistent with the overall style

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rusya
2025-08-30 21:11:51 +03:00
parent 649c4c56a4
commit 982f1a5fae
4 changed files with 11 additions and 11 deletions
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include/utils.h
+3 -3
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@@ -13,9 +13,9 @@ uint32_t fat32_datetime(uint16_t year, uint8_t month, uint8_t day, uint8_t hour,
//got these from osdev.org //got these from osdev.org
void cpuid(int code, uint32_t *a, uint32_t *d); void cpuid(int code, uint32_t *a, uint32_t *d);
bool cpuHasMSR(); bool cpu_has_msr();
void cpuGetMSR(uint32_t msr, uint32_t *lo, uint32_t *hi); void cpu_get_msr(uint32_t msr, uint32_t *lo, uint32_t *hi);
void cpuSetMSR(uint32_t msr, uint32_t lo, uint32_t hi); void cpu_set_msr(uint32_t msr, uint32_t lo, uint32_t hi);
#define inb inportb #define inb inportb
#define outb outportb #define outb outportb
src/kernel/apic.c
+3 -3
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@@ -44,12 +44,12 @@ void cpu_set_apic_base(uintptr_t apic) {
edx = (apic >> 32) & 0x0f; edx = (apic >> 32) & 0x0f;
#endif #endif
cpuSetMSR(IA32_APIC_BASE_MSR, eax, edx); cpu_set_msr(IA32_APIC_BASE_MSR, eax, edx);
} }
uintptr_t cpu_get_apic_base() { uintptr_t cpu_get_apic_base() {
uint32_t eax, edx; uint32_t eax, edx;
cpuGetMSR(IA32_APIC_BASE_MSR, &eax, &edx); cpu_get_msr(IA32_APIC_BASE_MSR, &eax, &edx);
#ifdef __PHYSICAL_MEMORY_EXTENSION__ #ifdef __PHYSICAL_MEMORY_EXTENSION__
return (eax & 0xfffff000) | ((edx & 0x0f) << 32); return (eax & 0xfffff000) | ((edx & 0x0f) << 32);
@@ -82,7 +82,7 @@ uint32_t lapic_read(uint32_t offset) {
} }
void lapic_eoi() { void lapic_eoi() {
lapic_write(LAPIC_EOI_REG, 0); lapic_write(LAPIC_EOI_REG, 0);
} }
void ioapic_init() void ioapic_init()
src/kernel/kernel.c
+2 -2
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@@ -46,12 +46,12 @@ void kmain(unsigned int magic, unsigned int info)
isr_install(); isr_install();
if(cpuHasMSR()) if(cpu_has_msr())
{ {
printf("CPU has MSR\n"); printf("CPU has MSR\n");
} }
if(check_apic() && cpuHasMSR()) if(check_apic() && cpu_has_msr())
{ {
printf("APIC is present\n"); printf("APIC is present\n");
lapic_enabled = true; lapic_enabled = true;
src/utils/utils.c
+3 -3
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@@ -65,19 +65,19 @@ inline void cpuid(int code, uint32_t *a, uint32_t *d)
const uint32_t CPUID_FLAG_MSR = 1 << 5; const uint32_t CPUID_FLAG_MSR = 1 << 5;
bool cpuHasMSR() bool cpu_has_msr()
{ {
static uint32_t a, d; // eax, edx static uint32_t a, d; // eax, edx
cpuid(1, &a, &d); cpuid(1, &a, &d);
return d & CPUID_FLAG_MSR; return d & CPUID_FLAG_MSR;
} }
void cpuGetMSR(uint32_t msr, uint32_t *lo, uint32_t *hi) void cpu_get_msr(uint32_t msr, uint32_t *lo, uint32_t *hi)
{ {
asm volatile("rdmsr" : "=a"(*lo), "=d"(*hi) : "c"(msr)); asm volatile("rdmsr" : "=a"(*lo), "=d"(*hi) : "c"(msr));
} }
void cpuSetMSR(uint32_t msr, uint32_t lo, uint32_t hi) void cpu_set_msr(uint32_t msr, uint32_t lo, uint32_t hi)
{ {
asm volatile("wrmsr" : : "a"(lo), "d"(hi), "c"(msr)); asm volatile("wrmsr" : : "a"(lo), "d"(hi), "c"(msr));
} }