start implementing APIC utils

src/kernel/apic.c

@@ -0,0 +1,79 @@
+#include "../include/apic.h"
+#include "../include/paging.h"
+
+#define IA32_APIC_BASE_MSR 0x1B
+#define IA32_APIC_BASE_MSR_BSP 0x100 // Processor is a BSP
+#define IA32_APIC_BASE_MSR_ENABLE 0x800
+
+#define LAPIC_ID_REG      0x020 // ID Register
+#define LAPIC_EOI_REG     0x0B0 // End-of-Interrupt Register
+#define LAPIC_SPURIOUS_REG 0x0F0 // Spurious Interrupt Vector Register
+
+#define PAGE_PRESENT         (1 << 0)
+#define PAGE_WRITE           (1 << 1)
+#define PAGE_WRITE_THROUGH   (1 << 3)
+#define PAGE_CACHE_DISABLE   (1 << 4)
+
+const unsigned int APIC_PAGE_FLAGS = PAGE_PRESENT | PAGE_WRITE | PAGE_WRITE_THROUGH | PAGE_CACHE_DISABLE;
+
+bool lapic_enabled = false;
+volatile uint32_t* lapic_ptr = NULL;
+
+bool check_apic()
+{
+    uint32_t eax, edx;
+    cpuid(1, &eax, &edx);
+
+    return edx & (1 << 9);
+}
+
+void cpu_set_apic_base(uintptr_t apic) {
+    uint32_t edx = 0;
+    uint32_t eax = (apic & 0xfffff0000) | IA32_APIC_BASE_MSR_ENABLE;
+ 
+ #ifdef __PHYSICAL_MEMORY_EXTENSION__
+    edx = (apic >> 32) & 0x0f;
+ #endif
+ 
+    cpuSetMSR(IA32_APIC_BASE_MSR, eax, edx);
+ }
+
+uintptr_t cpu_get_apic_base() {
+    uint32_t eax, edx;
+    cpuGetMSR(IA32_APIC_BASE_MSR, &eax, &edx);
+ 
+ #ifdef __PHYSICAL_MEMORY_EXTENSION__
+    return (eax & 0xfffff000) | ((edx & 0x0f) << 32);
+ #else
+    return (eax & 0xfffff000);
+ #endif
+ }
+
+ void enable_apic() {
+    /* Section 11.4.1 of 3rd volume of Intel SDM recommends mapping the base address page as strong uncacheable for correct APIC operation. */
+
+    /* Hardware enable the Local APIC if it wasn't enabled */
+    cpu_set_apic_base(cpu_get_apic_base());
+
+    printf("APIC base: 0x%X\n", cpu_get_apic_base());
+    map_page((void*)cpu_get_apic_base(), (void*)cpu_get_apic_base(), APIC_PAGE_FLAGS);
+
+    lapic_ptr = (uint32_t*)cpu_get_apic_base();
+
+    /* Set the Spurious Interrupt Vector Register bit 8 to start receiving interrupts */
+    lapic_write(0xF0, lapic_read(0xF0) | 0x100);
+}
+
+void lapic_write(uint32_t offset, uint32_t value) {
+    uint32_t volatile *ptr = (uint32_t volatile *)(lapic_ptr + offset);
+    *ptr = value;
+  }
+  
+uint32_t lapic_read(uint32_t offset) {
+    uint32_t volatile *ptr = (uint32_t volatile *)(lapic_ptr + offset);
+    return *ptr;
+}
+
+void lapic_eoi() {
+    lapic_write(LAPIC_EOI_REG, 0);
+}

src/kernel/isr.c

@@ -5,6 +5,7 @@
 #include "../include/pit.h"
 #include "../include/keyboard.h"
 #include "../include/task.h"
+#include "../include/apic.h"
 
 #include <stddef.h>
 
@@ -103,8 +104,14 @@ void handle_page_fault(uint32_t error_code, uint32_t faulting_address)
 
 __attribute__((interrupt)) void isr_timer(struct interrupt_frame *frame)
 {
-	pit_init(100);
-	pic_end_int(0x0);
+    if(lapic_enabled)
+    {
+        lapic_eoi();
+    }
+    else
+    {
+	    pic_end_int(0x0);
+    }
 
 	//scheduler_lock();
 	schedule();
@@ -115,7 +122,14 @@ __attribute__((interrupt)) void isr_custom(struct interrupt_frame *frame)
 {
 	//terminal_writestring("YOOOOO!!!!!! I LOVE KATYA!!!!");
 	handle_keyboard();
-	pic_end_int(0x1);
+    if(lapic_enabled)
+    {
+        lapic_eoi();
+    }
+    else
+    {
+	    pic_end_int(0x1);
+    }
 }
 
 void isr0()

src/kernel/kernel.c

@@ -14,18 +14,11 @@
 #include "../include/kheap.h"
 #include "../include/exec_from_file.h"
 #include "../include/atapi.h"
-#include "../include/lib9660.h"
 #include "../include/vfs.h"
+#include "../include/apic.h"
 
 #include <stdint.h>
 
-void apply_pic_masks()
-{
-	//0x21 is master pic, 0xa1 is slave pic
-	outb(0x21,0xfc);//0b11111100 (bit 0 is PIT, bit 1 is keyboard and so on)
-   	outb(0xa1,0xff);
-}
-
 void kmain(unsigned int magic, unsigned int info)
 {
 	struct multiboot_info mbi;
@@ -52,10 +45,30 @@ void kmain(unsigned int magic, unsigned int info)
 	printf("done\n");
 
 	isr_install();
-	pic_remap(0x20, 0x28);
-	pit_init(100);
 
-	apply_pic_masks();
+	if(cpuHasMSR())
+	{
+		printf("CPU has MSR\n");
+	}
+
+	if(check_apic() && cpuHasMSR())
+	{
+		printf("APIC is present\n");
+		lapic_enabled = true;
+	}
+
+	if(!lapic_enabled)
+	{
+		pic_remap(0x20, 0x28);
+		pit_init(100);
+
+		pic_apply_masks();
+	}
+	else
+	{
+		pic_disable();
+		enable_apic();
+	}
 
 	printf("done fucking with pages and memory map!\n");
 	char *test_str;

src/kernel/pic.c

@@ -75,3 +75,10 @@ void pic_end_int(uint8_t irq) {
   if (irq >= 8) outb(PIC2_COMMAND, 0x20);
   outb(PIC1_COMMAND, 0x20);
 }
+
+void pic_apply_masks()
+{
+	//0x21 is master pic, 0xa1 is slave pic
+	outb(0x21,0xfc);//0b11111100 (bit 0 is PIT, bit 1 is keyboard and so on)
+   	outb(0xa1,0xff);
+}

src/utils/utils.c

@@ -57,3 +57,27 @@ uint32_t fat32_datetime(uint16_t year, uint8_t month, uint8_t day, uint8_t hour,
 
 	return fat_datetime;
 }
+
+inline void cpuid(int code, uint32_t *a, uint32_t *d)
+{
+	asm volatile("cpuid":"=a"(*a),"=d"(*d):"a"(code):"ecx","ebx");
+}
+
+const uint32_t CPUID_FLAG_MSR = 1 << 5;
+
+bool cpuHasMSR()
+{
+   static uint32_t a, d; // eax, edx
+   cpuid(1, &a, &d);
+   return d & CPUID_FLAG_MSR;
+}
+
+void cpuGetMSR(uint32_t msr, uint32_t *lo, uint32_t *hi)
+{
+   asm volatile("rdmsr" : "=a"(*lo), "=d"(*hi) : "c"(msr));
+}
+
+void cpuSetMSR(uint32_t msr, uint32_t lo, uint32_t hi)
+{
+   asm volatile("wrmsr" : : "a"(lo), "d"(hi), "c"(msr));
+}